Microchip Technology /ATSAMV70N19 /SPI0 /CSR[3]

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Interpret as CSR[3]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CPOL)CPOL 0 (NCPHA)NCPHA 0 (CSNAAT)CSNAAT 0 (CSAAT)CSAAT 0 (_8_BIT)BITS0SCBR0DLYBS0DLYBCT

BITS=_8_BIT

Description

Chip Select Register (CS_number = 0) 0

Fields

CPOL

Clock Polarity

NCPHA

Clock Phase

CSNAAT

Chip Select Not Active After Transfer (Ignored if CSAAT = 1)

CSAAT

Chip Select Active After Transfer

BITS

Bits Per Transfer

0 (_8_BIT): 8 bits for transfer

1 (_9_BIT): 9 bits for transfer

2 (_10_BIT): 10 bits for transfer

3 (_11_BIT): 11 bits for transfer

4 (_12_BIT): 12 bits for transfer

5 (_13_BIT): 13 bits for transfer

6 (_14_BIT): 14 bits for transfer

7 (_15_BIT): 15 bits for transfer

8 (_16_BIT): 16 bits for transfer

SCBR

Serial Clock Bit Rate

DLYBS

Delay Before SPCK

DLYBCT

Delay Between Consecutive Transfers

Links

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